It would be interesting to know if oneAPI will provide some abstraction of tiled matrix processing that will be common between the new AMX CPU instructions and the XMX FPGA capabilities, as they have apparently made an attempt to do for SIMD operations.
I thought that was a typo, but no, that's really what it says on the slide. Any idea what format FP19 actually is? The only thing I could find on the internet is a roundabout description of Nvidia's new TF32 format being essentially a 19-bit floating point, but it would be good to get clarification on what they actually meant.
yeah, bfloat16 and tf32 ... Intel wants FPGAs as alternative backend for converted CUDA code in their oneAPI, so this is a good move by them to duplicate the tf32 data type.
This was probably the biggest surprise of the conference; Intel seems to have taken the lead of the fundamental innovation in logic and routing fabric whereas Xilinx seems content and focuses on adding hard blocks.
The "register everywhere" concept was introduced with Stratix 10. In traditional FPGAs, the routing fabric is purely combinatorial: signals in arrive logically in the same clock cycle, which implies that long routes constrain the cycle time. Stratix 10 added bypassable-flops on all(?) routing which suggests you can retime using those. Rumors claimed that in practice Quartus had a hard time taking advantage of this and they sort of hint at this with an insistence of a complete revamping of the software. Very cool stuff. (I'm not affiliated in anyway with any FPGA company and holds no positions).
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JayNor - Tuesday, August 18, 2020 - link
It would be interesting to know if agilex FPGAs are being used in the Aurora project.It would also be interesting to know if eASIC migration can be done from 10nm agilex designs and, if so, what process they are using.
JayNor - Tuesday, August 18, 2020 - link
It would be interesting to know if oneAPI will provide some abstraction of tiled matrix processing that will be common between the new AMX CPU instructions and the XMX FPGA capabilities, as they have apparently made an attempt to do for SIMD operations.alfalfacat - Tuesday, August 18, 2020 - link
"FP19"I thought that was a typo, but no, that's really what it says on the slide. Any idea what format FP19 actually is? The only thing I could find on the internet is a roundabout description of Nvidia's new TF32 format being essentially a 19-bit floating point, but it would be good to get clarification on what they actually meant.
whatthe123 - Tuesday, August 18, 2020 - link
if it's anything like nvidia's TF32 its FP32 but with only 10-bit mantissa. So 1 + 8 + 10 = FP19 for AI workloads.tommythorn - Tuesday, August 18, 2020 - link
1+8+10 was confirmed offline.JayNor - Wednesday, August 19, 2020 - link
yeah, bfloat16 and tf32 ... Intel wants FPGAs as alternative backend for converted CUDA code in their oneAPI, so this is a good move by them to duplicate the tf32 data type.tommythorn - Tuesday, August 18, 2020 - link
This was probably the biggest surprise of the conference; Intel seems to have taken the lead of the fundamental innovation in logic and routing fabric whereas Xilinx seems content and focuses on adding hard blocks.The "register everywhere" concept was introduced with Stratix 10. In traditional FPGAs, the routing fabric is purely combinatorial: signals in arrive logically in the same clock cycle, which implies that long routes constrain the cycle time. Stratix 10 added bypassable-flops on all(?) routing which suggests you can retime using those. Rumors claimed that in practice Quartus had a hard time taking advantage of this and they sort of hint at this with an insistence of a complete revamping of the software. Very cool stuff. (I'm not affiliated in anyway with any FPGA company and holds no positions).
JayNor - Wednesday, August 19, 2020 - link
yeah, Intel used hyperflex-2 in agilex.https://blogs.intel.com/psg/2nd-generation-intel-h...