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  • ToTTenTranz - Thursday, March 5, 2020 - link

    Aren't most long-living N7 products supposed to become N6 anyway?
  • dotjaz - Thursday, March 5, 2020 - link

    But AMD never used vanilla N7
  • extide - Friday, March 6, 2020 - link

    Um, yes it did. It even says so in the article:
    "however it is not explicity stating whether this would be N7P or N7+, just that it will be ‘better’ than the base N7 used in its first 7nm line."

    "base N7 used in its first 7nm line"

    Vega 20 must use it, and I believe the Zen2 CCDs do as well.
  • dotjaz - Friday, March 6, 2020 - link

    Nope vailla N7 has M1/BEOL scale of 1.0x and 13 metal layers, AMD used 1.45x and 14 layers, that's why AMD's N7 "Large Die" had half the density. Their GPU is even worse in term of density, they used 7.5T instead of 6T.

    So in summary compared to base N7, AMD's version has different gate/metal size, more metal layers, allows different track count, if you call that "vanilla" I don't know what's not "vanilla".
  • FreckledTrout - Monday, July 13, 2020 - link

    AMD never used/uses the initial new node from TSMC because those are always for low power ie iPhone chips etc. TSMC takes about 1 year to tweak said process for high power which you will see some density losses to allow higher frequencies.
  • AnGe85 - Friday, March 6, 2020 - link

    For example Vega 20 and Zen2 use N7.
  • dotjaz - Friday, March 6, 2020 - link

    No they don't. Zen2 use N7 "Large Die" which had different scale and metal layer count. Vega 20 goes further to use 7.5T library.

    NONE OF THOSE were offered in N7. Qualcomm used "high performance" N7 lib which only relaxed CPP from 54nm to 57nm
  • dotjaz - Friday, March 6, 2020 - link

    *57nm to 64nm
  • AnGe85 - Saturday, March 7, 2020 - link

    You are confusing manufacturing process (N7) with its associated cell libraries (e.g. H240 HD (6T) and H300 HP (7.5T)). Apples A12, A12X, the Kirin 980, Snapdragon 855 and AMDs Vega 20 and Zen 2 all use(d) TSMCs CLN7FF aka N7 process.
    Additionally density does not directly result from used libraries, instead it depends on the design goals. Vega 20 most likely used H300 HP, but for Zen 2 AMD switched to H240 HD. The Snapdragon 855 uses for the so-called prime core, a single, faster Kryo 485 Gold the H300 HP lib, but for all remaining seven cores and the rest of the SoC the H240 HD lib and still archives a much higher density than AMD with its chiplet, because the design goals have been different.
    Avg. MTr/mm2:
    Vega 20 = ~ 40
    Zen 2 = ~ 52
    SD 855 = ~ 91
    (To complete the wrap-up, there has also been a high performance H360 HP lib (9T) for the N7, which has become obsolete over time.)
  • AnGe85 - Friday, March 6, 2020 - link

    N7P (DUV only) and N7+ (4 layers EUV) are production-ready since mid 2019.
  • twotwotwo - Friday, March 6, 2020 - link

    TSMC's N7+ seemed like an odd next step, because while N7 was design rule compatible with N7P and N6, N7+ apparently had different rules so it would require a different physical implementation (https://fuse.wikichip.org/news/2567/tsmc-talks-7nm... ). Whatever this is, maybe it lets them reuse parts of their previous gen's implementation.

    On the other hand, this gen is supposed to be a new microarchitecture, so maybe it wouldn't have been *so* odd to implement it on a process with different design rules. We're all sorta wandering around in the dark trying to squeeze anything meaningful out of the little that's disclosed about the complicated mess of low-level design/manufacturing.
  • AnGe85 - Friday, March 6, 2020 - link

    There's nothing odd about it.
    TSMC first developed the N7 (DUV and multipattering). Then, as an advancement, they implemented the (partial) use of EUV and developed the N7+ with 4 EUV layers (with first tapeouts in Oct.'18). Then they started to optimize the N7 to N7P, still DUV based. Both, N7+ and N7P were ready for mass production around mid 2019.
    After that, they announced the N6 (five EUV layers), because they expect a lot of customers to stay on 7 nm processes for a longer period and they want to give them an easier opportunity to migrate from N7 or N7P (because the N7+ uses different design rules than the N7(P)).
  • lefty2 - Friday, March 6, 2020 - link

    Yep. N6 won't be in production until next year, which is why AMD can't use it for Milan or Navi 2X
  • jOHEI - Friday, March 6, 2020 - link

    N7P came at the same time as N7+, but it was only announced as such later
  • CiccioB - Saturday, March 7, 2020 - link

    N7P was probably plan B in case N7+ was not ready for mass production in time..
    and it seem it is not
  • Fulljack - Monday, March 9, 2020 - link

    I don't think TSMC has enough scale to produce N7+ chips at huge scale. Apple A13 and Qualcomm SD865 still use N7P manufacturing process, either because moving to N7+ prove too much of a hassle due to different design rules or TSMC couldn't mass production N7+ at Apple's or Qualcomm's scale.

    Currently N7+ are only used by Kirin 990 5G (the one with integrated 5G modem).
  • scineram - Friday, March 6, 2020 - link

    Didn't Shor say Navi is using N7P? This news does not help clarity.
  • Gondalf - Friday, March 6, 2020 - link

    Nobody want 7nm+ EUV this is a fact, TSMC have not big customers on it. Without good pellicles this process is a damnation.
    Very likely we will see a plain 7nm version of Zen 3 with less enhancements in performance than expected. Better be able to supply the customers than to have a faster SKU with no good availability form foundries.
    I remember that the real high volume pellicles for EUV will are available only at the beginning of 2021. This the reason Intel will be in volume on 7(5)nm EUV only at the end of 2021.
  • wolfesteinabhi - Friday, March 6, 2020 - link

    N7+ is more of a "test"/"proof" vehicle for their EUV .. before going full dive into it with 5nm ..so they continur to use N7 and N7P with DUV and can offer N7+ in some limited capacity .. they will have alot learnings that would have helped them to develop N5 in a good way.
  • Korguz - Friday, March 6, 2020 - link

    gondalf
    " Nobody want 7nm+ EUV this is a fact " post proof of this " fact "
    " Better be able to supply the customers than to have a faster SKU with no good availability form foundries. " like intel is doing with 14+++++++++++ and 10 nm ?
    " This the reason Intel will be in volume on 7(5)nm EUV only at the end of 2021. " yea ok sure, again, can you prove this ??
  • WaltC - Friday, March 6, 2020 - link

    Again, Papermaster was very clear on the fact that + improvement had been rolled into their 7nm standard production node, I thought--what I get from that is while 7nm is called +, it now includes many of the most important + features. Either Papermaster misspoke or else this 7nm is a better node than the first one--which would not be surprising at all.
  • CiccioB - Friday, March 6, 2020 - link

    I think AMD just hoped for 7n+ (EUV) to be ready for RDNA2 and Zen3 but they were not that lucky as for plain 7nm that ramped up quite well for them.

    So they just made a turn back and are now targeting the other <7nm options hinting that 7nm+ meant whatever after plain 7nm that is good enough
  • Fataliity - Friday, March 6, 2020 - link

    It's still on the same process. TSMC just renamed "7nm+" to "N7". There are multiple variants of N7 under the same node name. For example
    7nm HPC
    N7
    N7P
    N7+

    That doesn't mean that it's no longer 7nm+. It just means TSMC is no longer calling it "7nm+" So neither is AMD.
  • dotjaz - Friday, March 6, 2020 - link

    That's a load of sh*t and you know it. TSMC NEVER EVER EVER called any process "7nm+". AMD calls the improved 7nm "7nm+" just like when they called 12LP "14nm+". It has NOTHING to do with TSMC's naming scheme.
  • CiccioB - Saturday, March 7, 2020 - link

    This is not true at all.
    TSMC has ALWAYS make distinction between its N7 versions:
    N7 for the DUV plain version, 7N+ for the EUV version and only lately N7P for the improved 7N on DUV.
    The rest of the world, that does not use TSMC PP names to make people understand the kind of PP used has always used the terms 7nm for the plain version and 7nm+ for the EUV version.
    Look in the Internet about any article written with the word '7nm+' in it and see what they are referring to.
    This was going on since TSMC has announced they were using EUV for a version of their 7nm PP.
    Now, this identifiers used for the slide last year were clear: 7nm for plain, 7nm+ for the EUV version.
    7NP just came out lately, 6 months ago. Before it it didn't exists at all.

    What happened is simply that AMD targeted 7mn+ (that is TSMC N7+) for the next generation of their product but now that PP is not mature as they thought it would be, and in fact, TSMC has now created a 7NP version to improve plain 7nm (N7) a little bit without having to wait for 7nm+ (N7+) to be ready, which would improve over N7 much more than N7P.

    In the original slide that is dated 2017, a couple of years before 7NP was born, there was also a refer to 14nm+, that surely didn't meant 'anything after 14nm PP' as AMD want now us to intend its 7nm+.

    This change in AMD nomenclature is simply a way to mask the fact that they missed the 7NM+ rendezvous (not their fault, but still a miss in their written roadmap) and have to fall back to a less performer PP that is the patched N7 (N7P).
  • LedHed - Friday, March 6, 2020 - link

    Can you confirm that Zen 2 chips, like the 3950X, were made using the base N7 processing?

    You almost said this, but you never actually did. Is this the case?
  • dotjaz - Friday, March 6, 2020 - link

    Nope, they are using a modified version with very different scaling/density. N7 Large Die appeared on TSMC's PPT once and "Large Die" certainly don't mean it's actually large. Zen2 chiplets are smaller than many baseline N7/N7P/N7+ dies such as A13, S865, K990 etc
  • Fataliity - Friday, March 6, 2020 - link

    At the end of their financial analyst day, AMD reiterated when asked a question about this that yes, it's still on the same process, but TSMC no longer calls 7nm+ "7nm+", its all encompassed under the "N7" name. So they changed their nomenclature to match TSMC's nomenclature.
  • dotjaz - Friday, March 6, 2020 - link

    TSMC never called anything "7nm+" they can't change from what they never used.
  • dotjaz - Friday, March 6, 2020 - link

    "Our second generation 7nm (N7+) technology entered risk production in August 2018" straight from TSMC website. They didn't call it 7nm+ while referring to N7+ explicitly.
  • ksec - Friday, March 6, 2020 - link

    I find this sentiment very strange, I will have to dig up old information to prove my point, but working on top of my head

    AMD clearly stats 7nm+ means 7nm EUV. That was written on their roadmap somewhere. It wasn't the confusion of N7+ or N7P. I think this is a spin that tries to control expectation.

    I think it is likely AMD at least intend to use 7nm EUV for Zen 3 at first, but their just isn't enough capacity AMD would like, and sticking to a more mature N7P and later N6 would be a far better option.
  • dotjaz - Friday, March 6, 2020 - link

    Where did they "clearly stats" 7nm+ means 7nm EUV and even if that were the case, why would that be N7+? AMD never used N7, they used N7 "Large Die", with 1.45x M1/BEOL scaling instead of 1x and so on, very different from the baseline N7.
    Why would AMD transition to an IP incompatible version (N7+ based) when by then, the IP compatible version of 7nm, N6 would be available?
  • scineram - Thursday, March 12, 2020 - link

    Because it is not.
  • eastcoast_pete - Saturday, March 7, 2020 - link

    Why does it even matter if AMD's chiplets are made using EUV, some EUV, or DUV, unless that makes a significant difference in power consumption or thermals thus justifying the costs? EUV is definitely here (ASML sold enough EUV scanners to validate that), but the yield is still way below DUV. Thus, it makes sense to Fab chips where power consumption is critical (smartphone SoCs etc) all or in part with EUV, and desktop CPUs and GPUs with the best compromise between cost (yield) and power consumption.
    Regarding desktop and laptop AMD CPUs and APUs, I expect the biggest improvements in power consumption to come from more efficient interconnects.
  • JKflipflop98 - Sunday, March 8, 2020 - link

    It would be almost impossible to fab a true 7nm part without EUV. You'd need octuple patterning at the contacts. This just goes to show how far from 7nm they really are. Their 7nm is more like 16 or so.
  • scineram - Thursday, March 12, 2020 - link

    No.
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