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  • CajunArson - Friday, January 24, 2020 - link

    Not only is Intel inside CHiP's, they even release a slick promo video showing how they can merge onto the superhighway of connectivity!

    https://www.youtube.com/watch?v=D5-bD372v5s
  • HStewart - Friday, January 24, 2020 - link

    Very funny, at least it was not horrible remake movie.
  • edzieba - Friday, January 24, 2020 - link

    I was sure they did this almost two years ago: https://fuse.wikichip.org/news/1520/intel-opens-ai... ? Unless the DARPA CHIPS program and the CHIPS Alliance are two identically named entities with the same function but not actually the same thing.
  • CharonPDX - Friday, January 24, 2020 - link

    They are indeed very similar, with identical names - but are completely different programs.

    DARPA CHIPS: Common Heterogeneous Integration and IP Reuse

    CHIPS Alliance: Common Hardware for Interfaces, Processors and Systems

    Similar goals, different organizations.
  • Hulk - Friday, January 24, 2020 - link

    Please forgive my unfamiliarity with this topic...

    What devices would we see the benefits of this technology and what would the real world benefits be?
  • HStewart - Friday, January 24, 2020 - link

    I think the main benefits are that chips with different technology can combine together in a chiplet that small and extremely fast - this can most be shown in i8705g which combines a Intel CPU with AMD designed GPU along with 4G of high speed memory. This can be found in laptops like the Dell XPS 15 2in1
  • name99 - Friday, January 24, 2020 - link

    The question is, are we going to see much of this:
    (a) connecting together chiplets from DIFFERENT vendors (so that standards are necessary) AND
    (b) for the purposes of devices that "you and I" care about (so no FPGAs and suchlike).

    For (a) people assume something like the ARM ecosystem will arise. But I'm not sure how varied the ARM ecosystem TODAY is. It looks to me like people get one collection of IP from ARM (CPU, maybe GPU, maybe NPU) and the rest is their stuff. In other words there's not much "multi-party" co-ordination necessary. In the ARM space, are there really people getting logic from ARM, memory controller from somewhere else, USB controller from somewhere else, ..., so that there's actually 5 IP sources that need to be co-ordinated?
    (And even if there, they all co-ordinate to what ARM says; no consortium necessary).

    For (b) obviously the current chiplet champion is AMD. All internally sourced. One day, supposedly, Lakefield and Foveros will ship, but again all internally sourced. At some point presumably Apple will ship chiplets -- maybe for their desktop ARM, maybe for Apple RF on separate silicon from Apple SoC -- but again all internal.

    It's easy to make up a story about how great mix-and-match chiplets will be. It's a little harder to connect that to reality once you consider what most people actually need and want from their computing. It's always nicer to put everything on a single SoC, and it's hard to come up with cases of separate chiplets that correspond to independently developed IP.

    Your Intel example is cute, but of course those were CHIPS, not CHIPLETS, that were packaged together. Will it happen again at the chiplet level?
    Part of me thinks that something like PCIe, while nice as a common standard, is also SLOW to develop, being a common standard... Will people stick with the spec from 3 years ago, especially if they don't need to because all their parts are internally sourced?
    And then we get that the AMD chiplet won't talk to the Intel chiplet bcs Intel is using the spec from 3 yrs ago, AMD has moved on, and there seemed no reason for them, at design time, to stick with the spec.
  • mode_13h - Saturday, January 25, 2020 - link

    Why (b)? You're basically excluding the whole embedded market, which I think is one of the main sectors they're targeting.

    While Apple has volumes & margins big enough to justify a monolithic die, a lot of embedded SoCs are more niche, and would find it more cost-effective to use pre-made chiplets to suit their needs.
  • rahvin - Friday, January 24, 2020 - link

    Think of it like the ability to add co-processor to a CPU.

    Something like an AI chip that's got a hi-speed interface with the CPU allowing the CPU to offload compatible tasks to the AI chip without the huge latency that would normally happen.
  • HStewart - Friday, January 24, 2020 - link

    the chip in my Dell XPS 15 2in1 had the CPU, Discrete AMD GPU and memory on it. But it could have an AI chip - it really does not matter and does not required the same process for each component.
  • name99 - Friday, January 24, 2020 - link

    This is precisely the scenario I DON'T buy. If you want an NPU, stick it on the damn SoC. There is only downside, zero upside to having it as a separate chiplet.

    Chiplets mainly worls for separate physical substrate.
    So
    - RF (but that's already handled by separate chip, chiplet just gets you a little power/space savings),
    - optical (people been talking about this for years, but if you can get Si photonics to work, again on SoC is better)
    - MRAM (maybe maybe maybe? but we've all been burned by talking up the eminent arrival of MRAM in consumer products)
    - cheaper IO hub ala AMD (this is the one realistic case --- but also the case that is least likely to require standardized connectivity...)
  • Kakti - Saturday, January 25, 2020 - link

    The obvious usecase based on the diagram provided is for self-driving cars or perhaps industrial manufacturing equipment such as CNCs and robotic welding tools. This is an interconnect to link a variety of sensors to the processing CPU, with inputs coming from:

    1) Analog front end (operator touchscreen and physical buttons)
    2) RF (radio frequency) reception/broadcast (cars or tolls talking to each other over low power maybe?)
    3) Sensors (water, air pressure, sudden acceleration/deceleration, etc),
    4) Video (back up cam amongst other uses)
    5) Thermal (checking battery/capacitor/ICE temperatures)
    6) Lidar (self-driving support, used by several Tesla competitors). Radar uses radio waves to bounce an electromagnetic signal off an object and counting the time it takes to return to calculate distance/speed, LIDAR uses optical lasers instead of radiowaves.
  • Fataliity - Friday, January 24, 2020 - link

    I see this being used for Hyperscalers. Platinum members are Ali, Google, etc.

    They can put their TPU connected directly to Intel CPU on substrate. Same wiht Ali's new Samsung AI accelerator. And Intel's Habana Labs AI solution.

    They're already making their own silicon. Why not keep yourself in the loop by being the CPU they decide to connect to? SiFive's in there. So if Intel doesn't do it, ARM/RISC will.
  • mode_13h - Saturday, January 25, 2020 - link

    Those guys also make embedded solutions, even if you mostly think of them as playing in the cloud.
  • alufan - Sunday, January 26, 2020 - link

    clever move making sure Intels chips are not designed out of the landscape, this is the way AMD needs to start thinking because everything that Intel does (rightly) ensures they are always a consideration for future designs. As a potential shareholder it would impress me the amount of forward thinking they demonstrate
  • NikTerry - Friday, February 28, 2020 - link

    Hello there,

    Does anyone know where can i find some more deatild specs for the AIB blocks?(AFE or SerDes)

    Thank you
    Nik
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