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  • abufrejoval - Wednesday, December 4, 2019 - link

    With Via's Centaur and the Nervana on a 'last generation node' I wonder if it's time to talk about a 'More's rebound'... It almost seems like a common perception that die shrinks aren't paying off any more.
  • Dragonstongue - Wednesday, December 4, 2019 - link

    Moore's actually if this what you are referencing, unless is "play on words" as in, wow those are stonking large GPU sized objects.. as they certainly are that, though to the first one, no, not really as the "law" has morphed many times over the years, in regards to transistor count doubling once every X time frame where now it is "easy" as they can just go MCM (or chiplet) so in effect are still "able" to be on the same cadence.

    I imagine once they start in the optical interconnect and/or Quantum style, these will likely be very very small jumps in comparison to what becomes the "very first" initial release of..not that you asked, from my reading here and there, they can "easily" go back to the 100s of nm size (as in microns, not nano meters)

    as they (optical and/or quantum) not neccersarily play by the same "base rules" are the current silicon based chips / substrate, so they get to start "all over again" which if they were smart, they would do and likely will do exactly this, why start at the very top of the ladder with no real place to go, when you can scale up over many years if not decades as they have done "in the past" which they still pretty much are (though that road is likely to be coming to an end quite soon enough)

    (^.^)
  • abufrejoval - Thursday, December 5, 2019 - link

    You caught me snitching an "o" from Gordon, most likely I was named after Sir Thomas More, the lord chancellor of Henry VIII..

    But it looks like others were surprised by the 16nm TMSC fabbing, too:
    https://www.servethehome.com/intel-nervana-nnp-l-1...

    Wouldn't it be nice, if one could get the full story on that.

    Among my theories are:
    1. Intel Fab issues vs. Facebook wanting a product at guaranteed deadlines
    2. Power consumption is a much bigger issue at inference because of its scale
    3. With the amount of scale-out required to train larger and larger networks, the chip designs become pad bound for all those SerDes anyway, at least until you have truly energy efficient optical links
  • edzieba - Thursday, December 5, 2019 - link

    "It almost seems like a common perception that die shrinks aren't paying off any more. "

    That's been the case for many years now, generally since 22nm (where gate oxide thickness hit the 1.3nm limit and prevented further transistor scaling, and where 'Xnm' process naming diverged from any real relation to feature size, and beyond which finFETs became necessary).

    Process shrinks have produced worse cost/transistor, worse cost/area, and lower maximum operating frequency. The only gains are in transistors/area and perf/watt, so there are only certain applications where it makes sense to move to a newer process: if you are already at the reticle limit and need to go bigger on a single die, or where performance is secondary to power consumption or you are otherwise limited by absolute power output more than operating frequency (i.e. thermally limited). And this scaling is only going to get worse as processes move to EUV and cost/transistor rises even more sharply. This is couple dwith the practical frequency cap introduced by the minimum gate oxide thickness (whey everyone has moved to scaling by adding more cores instead) meaning you need to add yet more transistors.
  • p1esk - Wednesday, December 4, 2019 - link

    Do you know anything about prices or actual performance of these cards?
  • Dragonstongue - Wednesday, December 4, 2019 - link

    likely not be at all low cost, as they reference Supermicro and "custom" more or less.

    also AI Tensor cores and Tbps speed bi-directional links.

    I imagine would be / likely will be very fast (for the custom work they need them for)

    likely in the many K per unit, all told 2P size (or more) guessing here, in the 20s of K $$ (not to mention custom everything else as well)

    wonder their overall power consumption per "rack" and/or cooling required to keep "@ spec"
  • p1esk - Wednesday, December 4, 2019 - link

    They gotta be significantly cheaper and/or faster than equivalent supermicro servers with V100.
  • colonelclaw - Thursday, December 5, 2019 - link

    One thing I do know about Supermicro kit, having ordered and built a whole load of it myself, is that it's normally significantly cheaper than the opposition. E.g. our current server cost us £12k as opposed to £20k for the exact same spec from Dell.
  • brucethemoose - Wednesday, December 4, 2019 - link

    What Intel needs is a dedicated single socket CPU platform with a boatload of PCIe lanes (128? 192? 256?) and 8+ memory channels, as AI workloads don't necessarily need much CPU grunt.

    I bet those 4P and 8P setups in particular have mostly idle cores, while the memory controllers are burning tons of power moving and syncing data between nodes.
  • Santoval - Thursday, December 5, 2019 - link

    "This is supported by 32 GB of HBM2-2400 memory, and technically the PCIe connection is a PCIe 4.0 x16 connection, however Intel does not have CPUs to support this yet."
    Then why mention PCIe 4.0 in their presentation images as a feature? Is this intended to be paired with Intel's current Xeon CPUs or their future Ice Lake Xeon CPUs that will support PCIe 4.0? If it's the former then the images are misleading. It would be like gluing a PCIe 4.0 supporting GPU to a PCIe 3.0 only motherboard and then citing PCIe 4.0 as a feature. A feature that can never be used.
  • Ian Cutress - Thursday, December 5, 2019 - link

    Correct.
  • Gondalf - Thursday, December 5, 2019 - link

    You are right. In last few years most advanced Intel server cpus are at big farms first (two quarters first) then common mortal volume shipment.
    Not surprised Facebook already has Ice lake SP on racks with PCIe4 running and Cooper Lake 56 cores from a long time for other applications.
  • The_Assimilator - Thursday, December 5, 2019 - link

    "acquisition with Nervana"

    I believe you meant "of".
  • name99 - Friday, December 6, 2019 - link

    Ian, how do you square all this happy talk of Nervana (and the more specialized Movidius and Mobileye) with the acquisition of Habana?
    What does Habana bring to the table that INTC doesn't already have? (For example, is Habana known to provide much better support for Transformer type architectures compared to anything Intel currently has?)
  • nn68 - Friday, December 13, 2019 - link

    My guess is, software. Habana Labs seem to have a pretty solid portfolio of libraries and whatnot.

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