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  • drwho9437 - Friday, September 10, 2004 - link

    Eskimo I was jus being sloppy in my language. As I progressed. Its good to know I'm not totally nuts. The resists will be a problem because of chain length. I mean for positive resists it seems ovious as it seems to be the ratio of the native to the broken resist chain length that would matter (there solublity). For a negative resist I guess you could somehow have some very simple and short chain somehow but I would think it would still need to be of the order of nm in length. I think it will be interesting if intel or someone else can reach high yeilds on structures of 5-10nm size. That would make SETs or other quantum devices useable in the millions.
  • KristopherKubicki - Friday, September 10, 2004 - link

    ceefka: Intel is actually moving in the other direction - particularly for server products. The Memory controller is in fact getting its own tunnel on chipsets like Twin Castle. I suspect this is being done so that they can incorporate multiple memory controllers on a single motherboard.

    Kristopher
  • ceefka - Friday, September 10, 2004 - link

    Great article, Kristopher.

    7 + 17 Right on! Seems like all they're doing is shrinking, more cache and pumping the FSB.

    Where is that on die memory controller?

    It doesn't seem like much of an animal if you keep it in a cage. What they're doing at Intel is great in itself, but it needs something extra.
  • Eskimo - Thursday, September 9, 2004 - link

    #13/#14, You are correct we are now entering the arena where the actual polymer chains which make up our resists are approaching some of the features that are being printed on the wafers. As for etching keep in mind that we don't actually etch the resist. Resist after exposure is developed away in an aqueous solution. The remaining resist serves as a mask for the underlying material either protecting from ion bombardment or etches. The standard etch for today's high aspect ratio features is Reactive Ion Etching (RIE). The 193nm resists in use in leading edge lithography do not have the same etch protection capabilities that were present in DUV(248nm) and i-line(365nm) resists. A new challenge for resists is posed by the upcoming widespread adoption (even Intel might come around) of immersion lithography where the resist will be directly exposed to water in the scanner.

    As for the article itself, it seems to suggest that Intel came up with the idea of phase shift masks. When in fact they were developed in the late 70's and first put into use in the early 90's by a variety of companies. The only real news on this front is that to reach 65nm on 193nm dry systems you will definately need alternating aperature phase shift masks like the diagram describes which are very costly.

    As for the statement saying Intel did not specify what sort of oxide they are doping with carbon for their low-k dielectric it is Silicon Dioxide. Since SiO2 is so prevalent in silicon processing and so well understood we often just refer to it simply as oxide. If it was in fact another material oxidized that would've been specifed (e.g. Aluminum Oxide).

  • mkruer - Thursday, September 9, 2004 - link

    #7 Read again what I wrote, I mentioned nothing abut the SPEED, working faster =! Speed in MHz which you are apparently inferring. I was simply stating that obvious that Intel solution for the majority of its problems is to simple through more cache at it.
  • GodsMadClown - Thursday, September 9, 2004 - link

    I remeber going to a talk on the Chandra X-Ray telescope and hearing about all the craziness with mirrors that they had to go through to get the optics to work. I guess that Intel could do the same thing, but It's just getting crazy. No real content, but to make everyone aware that when you deal with EUV radiation, optics get very complex.
  • stephenbrooks - Thursday, September 9, 2004 - link

    I'm pretty sure that on the last page it should be "line width" going to 0.7x every two years, not line LENGTH! Total line length on a chip should increase 1.4x every two years because they're packing it in smaller.
  • drwho9437 - Thursday, September 9, 2004 - link

    To clarify, I mean you have to etch the resist, dry or wet, you have to do it and that has some limit, but I don't know what it might be or even what kind of etching big fabs use.
  • drwho9437 - Thursday, September 9, 2004 - link

    Humm. Aren't we going to hit the limit of resists soon? I mean the resists I know about for ebeam lithography have resolution of something like 8nm. Intel is going to do 23 with photolithography, that's impressive, you can always go to x-rays if all it was was a matter of making the photon wavelength sorter but what about the chemistry? (I'm not a chemist, I'm a physicist/EE)
  • ncage - Thursday, September 9, 2004 - link

    I read the other post and thats what i used as my reference to spell it. Dumb idea i guess ;)
  • RyanVM - Thursday, September 9, 2004 - link

    I'm trying to figure out if you guys are using "Itanimum" because you're trying to be witty or just don't know that its name is "Itanium". I think my sarcasm meter might be broken.
  • mrmorris - Thursday, September 9, 2004 - link

    Interesting article, looking forward to getting "the big picture" when Intel competite technology is included (AMD).
  • PrinceGaz - Thursday, September 9, 2004 - link

    1T-SRAM is basically DRAM with a built in controller that handles all the refreshing etc, so it can be used in a similar way to SRAM.

    Because it uses DRAM technology, its nowhere near as fast as true SRAM and therefore unsuitable for use as cache memory.
  • Skykat - Thursday, September 9, 2004 - link

    As I recall, the Nintendo Gamecube uses 1T-SRAM (1 transistor). Whatever happened to this technology? It would seem a lot more efficient than 6 Transistor SRAM. I think the Gamecube processor was manufactured by IBM though...
  • ncage - Thursday, September 9, 2004 - link

    #5 speed is NOT the ideal thing for what itanimum was made for. Itanimum is made for high end servers where caching is just as important as speed. Think of the high end scientific apps where the majority of the work is swapping data back and forth from ram to peform calculations on. Ya they could speed up the cpu but it would be cache starved and would be ide wile it was waiting to fetch data from main memory into cache/registers. Lots of cache is also ideal for large database appliations. One thing i am suprised is intel has not decided to go with an on die memory controller like AMD.
  • mkruer - Thursday, September 9, 2004 - link

    When I said double up on the logic I meant parallel processing, not making the logic more complex.
  • mkruer - Thursday, September 9, 2004 - link

    I will not say that I am disappointed, but I think I could sum this article up much faster, Intel has Awesome FAB capabilities, but too bad their chip designs are not the greatest. One day Intel might lean that instead of throwing huge amounts of cache to get everything to work faster, to double up on the logic. Just imagine if the Itanimum was cache efficient, with the amount of chip real-estate they could save they could easily double the core logic, and get a true boot in performance.
  • nourdmrolNMT1 - Thursday, September 9, 2004 - link

    i agree with number 3.

    MIKE
  • CrimsonDeath - Thursday, September 9, 2004 - link

    Wow i feel really stupid right now...
  • Johnmcl7 - Thursday, September 9, 2004 - link

    Yeah, I fully agree I was a little disappointed the article seemed to end rather abruptly, however it was an interesting read otherwise.

    Also, shouldn't it be 'extensions of Moore's Law' rather than 'extentions'?

    John
  • mikecel79 - Thursday, September 9, 2004 - link

    Great article on Intel's technology but why nothing about the dual core P4 they showed running on a 915 board yesterday?

    From the ZDnet article at http://zdnet.com.com/2100-1103_2-5356703.html

    "Like the current Pentium 4, Intel's dual-core desktop chip is built on the NetBurst architecture and fits into motherboards using Intel's 915 Grantsdale chipset. But Siu declined to provide many details on the dual-core demonstration chip, which he described as an engineering prototype.

    "It is real silicon running on a standard 915 platform," Siu said. He wouldn't comment on whether it has the 64-bit memory extension technology, called EM64T."

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