Oh Samsung, you really need to hire better marketers. OBVIOUSLY the correct name should have been "Abundant Bridge Channel FET" or abcFET!
More seriously, how plausible is this "variable width" claim? A few years ago I saw similar claims regarding finFET height, and I believe TSMC even created a demo chip showing this. (Here's a patent that sorta covers part of the tech: https://patents.google.com/patent/US20150262861 ) But as far as I know this possibility has never been exploited in the mainline processes of any fab.
Obviously the geometry is somewhat different, which may make variable width cheaper than variable height. But the fact that Samsung isn't highlighting this makes me wonder if it's the sort of degree of freedom that sounds good in principle, but is not actually that useful in practice?
They had more detail on it in the afternoon talks. Their PDK comes with four variable width options that are optimized so far, so it's more than just being hopeful. If I can get the slides from the main presentations I'll write something up about it.
Perhaps I wasn't clear? The difference is between "continuously variable" and "discretely variable". If you have four discrete widths is that so different from today where you might use two fins for low speed logic and maybe up to five fins (or more) for either high speed or to drive pins?
Is the significant difference that the gradations are substantially smaller than the "per fin" gradations we see today, so that even discrete width differences allow one to optimize slightly closer to the ideal drive current for that particular circuit?
It remains unclear to me if the number of vertical sheets is a second independent variable (so that today's equivalent of coarse steps will be anything from 2 through 5+ sheets, with width providing a fine adjustment to the drive current) or if three sheets (or whatever) is pretty much baked into a particular process and ALL the variation is via the widths.
And how much is this ability to approach the ideal drive current (whether small discrete steps, or continuous variation) worth? 5% in reduced power or 20%?
You're troll and a hater. Are you an engineer? are you a PHD ?? If you are so right why don't you write an academic paper and submit it, if you are so right? 3nm was a major feat. Something people thought was not possible. But they did it. TSMC is just good at FinFit. After that, what? They are better than Samsung at Fin-fit. Samsung went Right into EUV. It was a mistake. But they knew it was going to be that way. Samsung was making stuff for Apple and everybody way before TSMC. Screens, which nobody can make. LCD. Which Taiwan didn't do until they followed the Koreans. Stop being a troll. Just have a positive tone. and Give them credit for doing something extraordinary. I don't know, people like you and your tone man. you can't say things without that tone? It's disgusting
Are you suggesting that they didn't do it? usfull in practice, This technology has been around for a long time. They did it. If it was not don right i'm sure all the scientists would have jumped at Samsung. Well we will see. All I know is that Samsung was the first to use EUV right away. Went straight into into. Didn't work out; But it seems it is going in that direction. This new things that they did. In my opinion, it noteworthy. They did it before anyone. I gues like folding phones. Of course it din't work out at first, but why didn't any body else who claimed they had it release their phones? Probably because they get all their display parts from Samsung. There would be no Huawei without Samsung. They could buy it from their cousins at BOA. Go ahead and see how many people buy your phone.
Wait their S10 Soc was still 8nm(which was supposedly 10nm with some improvements) and so they are planning 7,6,5,4 and 3nm over next 2 years !!!!! Do we know if Note 10 SOC will atleast use 7nm EUV process.
Samsung claim that they started fabbing something (undisclosed) in high volume 7nm towards the end of 2018. There are a few reasonable possibilities, like Tesla (their chip is Samsung, nothing more disclosed) or maybe one of the various NN companies that have sprung up.
5nm and 4nm are somewhat like 7nm+ and 7nm++, so reasonable products for say late 2019/early 2020 and mid 2021. Then 3nm late 2022. It's not an unreasonable schedule.
Samsung is not (as far as I know) discussing a 6nm. That's TSMC, for whom 6nm is more or less their 7nm++ for next year (7nm+ is this year's process). It will run in parallel with TSMC 5nm, but of course these are foundries --- part of their business model is to run simultaneously multiple processes at different performance/cost tradeoffs.
Don't forget that as EUV matures it will be involved in more of the process steps which is hopefully where a lot of these gains will come from. EUV was still extremely expensive when 7nm first launched to it was used in very few "bullet-proof" steps.
You are taiwanese arn't you? You guys are funny. Samsung and Hynex was bust with their supercycle with their dram and nand chips. EVU Samsung went right into. TSMC Still using FINFIT. Just using EUV here and here. Don't get too Cocky dude. Samsung jsut went made a revolutionary feat which was in very much doubt. Stop being a troll because you are jealous. Just give them what they deserve. They accomplish something. That's it. You tone sucks and you're angy Samsung got there before Taiwan. EUV right away didn't work wout. But after the supercycle, they will cocentrate on the SOC which they already have. I didn't hear TSMC doing anything with EUV before Samsung brought it in. So just stop being a troll
They cannot be compared via nm numbers because these are purely marketing numbers. One more objective way of comparison is via transistor density, i.e. the number of transistors per mm^2. Even that can be fudged though, because for instance SRAM caches have different transistor density than the logic part of a chip. An ideal way of third party comparison of the density of different nodes would be to compare the density of the exact same chip (CPU or GPU) fabbed at say 14nm and 7nm. If you know the total number of transistors of the chips (which should be identical) you can then measure the bare dies to calculate their size (in square mm) and then divide the total transistor number by the die sizes to get the transistor density per mm^2.
In some ways you can think of Samsung 3nm here as Samsung 7nn++++. But the real determination is the number of transistors per size and speed between each device. Not sire if other foundries will have something similar to Intel Foreros which is not to confused with EMiB, where the die is 3d direction which increases the components in the vertical direction.
I believe a storm is coming with this technology, it does not mean that this 3nm will be replace, but it could mean one of component in the Foreros package could be 3nm based - say if Samsung comes out with dense ram chips.I believe that Foveros is a revolution not evolution in technology. But it is designed to complement the process technology not replace it.
Foveros is NOT a revolution. It is just 3D stacking. The most impressive part of it is the moving of a cache layer to the active interposer-ish base that the chiplets are attached to for it. Other than that, it is just the evolution of 2.5D, which AMD has had whitepapers detailing the analysis on cost of implementation back around November or December of 2017.
So, to have something competitive, all they would need to do is incorporate components of their I/O die onto the active interposer and place HBM centrally stacked with the core chiplets around. Now, Intel being able to stack eDRAM for a level 4 cache sitting above the hotter components is a step forward, but other companies have looked into that as well and the entire industry has been moving toward that. They don't have a major lead on anyone in that regards. Also, they are only using it at first in extremely low power devices, which is where heat from core chiplets is easier to manage. Implementation in high performance chips will take more time because of that.
So, a 2.5D will likely be used in a high performance setting before 3D integrations. Whether Intel, AMD, or some other player will do so is just a matter of seeing who wins that race. But this isn't as revolutionary as you make it seem. It is an incremental step.
The names are marketing, they don't refer to any specific aspect of the process. We don't know how this will compare to Intel's nodes, they haven't said nearly as much as Samsung.
"The headline PPA values that Samsung is announcing are also impressive: compared to 7nm, 3GAE will offer 1.35x performance, 0.5x power, with a 0.65x die area."
If the area is down 45%, then the die area is surely 0.55x, not 0.65x?
Also I guess that die area shrink is for the thinnest bridges. Ditto the power.
The 35% performance improvement is significant for a shrink these days. I guess that's for the widest bridges of course.
Yeah but different products have different uses. Maybe it need the temperature. Maybe it needs the power. Just because it mutually exclusive doesn't really mean anything. All I can say was this is the first crack at it. When you first did something were you the best? were you able to perfect everything there was; NO !!!! But Samsung just pulled off something extraordinary. Let's leave it at that. You have to remember people thought this was impossible. But they did it. That is what i am impressed with. I love computers. I majored in Econ, and it was a good major, but computer are the next revolution. Sometimes, I wished I studied computers.
It's crazy, there was this standstill at 28nm, and another one at 14nm where it seemed like any further improvements would be minimal, yet here we are in a whirlwind of constant developments that seem to be coming faster and faster.
Not really, apparently 7nm would be 4x the density of 14nm right, that didn't happen, and this 3nm is not ~5.4x density of 7nm. The numbers are bumping, that's for sure.
Yeah, but you're comparing Finfit which is the same technology to Gate all around. a quiet different technology. In addition, this is Beta 1. The important thing is that is was done. Something many thought was impossible. Comparing tow different technology is not fair
But this will break the law. Moors law, which is quiet significant. But i fully agree. Someone has to figure it out. The reward is the recognition, respect and of course the MONEY.
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32 Comments
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name99 - Tuesday, May 14, 2019 - link
Oh Samsung, you really need to hire better marketers.OBVIOUSLY the correct name should have been "Abundant Bridge Channel FET" or abcFET!
More seriously, how plausible is this "variable width" claim? A few years ago I saw similar claims regarding finFET height, and I believe TSMC even created a demo chip showing this. (Here's a patent that sorta covers part of the tech:
https://patents.google.com/patent/US20150262861 )
But as far as I know this possibility has never been exploited in the mainline processes of any fab.
Obviously the geometry is somewhat different, which may make variable width cheaper than variable height. But the fact that Samsung isn't highlighting this makes me wonder if it's the sort of degree of freedom that sounds good in principle, but is not actually that useful in practice?
Ian Cutress - Tuesday, May 14, 2019 - link
They had more detail on it in the afternoon talks. Their PDK comes with four variable width options that are optimized so far, so it's more than just being hopeful. If I can get the slides from the main presentations I'll write something up about it.name99 - Tuesday, May 14, 2019 - link
Perhaps I wasn't clear? The difference is between "continuously variable" and "discretely variable".If you have four discrete widths is that so different from today where you might use two fins for low speed logic and maybe up to five fins (or more) for either high speed or to drive pins?
Is the significant difference that the gradations are substantially smaller than the "per fin" gradations we see today, so that even discrete width differences allow one to optimize slightly closer to the ideal drive current for that particular circuit?
It remains unclear to me if the number of vertical sheets is a second independent variable (so that today's equivalent of coarse steps will be anything from 2 through 5+ sheets, with width providing a fine adjustment to the drive current) or if three sheets (or whatever) is pretty much baked into a particular process and ALL the variation is via the widths.
And how much is this ability to approach the ideal drive current (whether small discrete steps, or continuous variation) worth? 5% in reduced power or 20%?
saratoga4 - Wednesday, May 15, 2019 - link
Continuously variable like planar transistors, so different than the discrete finfet sizes. Should save some area.justaviking - Wednesday, May 15, 2019 - link
"Oh Samsung, you really need to hire better marketers.OBVIOUSLY the correct name should have been "Abundant Bridge Channel FET" or abcFET!"
How about...
Best Optimization for Best All-around FET.... BobaFET
name99 - Wednesday, May 15, 2019 - link
Sir, today you win the internets and my admiration!Rοb - Monday, June 17, 2019 - link
MBCFET is from 2003: https://ieeexplore.ieee.org/document/1264877 - Also, it's BoboFeet: https://static.comicvine.com/uploads/scale_small/0...attila123 - Sunday, January 19, 2020 - link
You're troll and a hater. Are you an engineer? are you a PHD ?? If you are so right why don't you write an academic paper and submit it, if you are so right? 3nm was a major feat. Something people thought was not possible. But they did it. TSMC is just good at FinFit. After that, what? They are better than Samsung at Fin-fit. Samsung went Right into EUV. It was a mistake. But they knew it was going to be that way. Samsung was making stuff for Apple and everybody way before TSMC. Screens, which nobody can make. LCD. Which Taiwan didn't do until they followed the Koreans. Stop being a troll. Just have a positive tone. and Give them credit for doing something extraordinary. I don't know, people like you and your tone man. you can't say things without that tone? It's disgustingattila123 - Sunday, January 19, 2020 - link
Are you suggesting that they didn't do it? usfull in practice, This technology has been around for a long time. They did it. If it was not don right i'm sure all the scientists would have jumped at Samsung. Well we will see. All I know is that Samsung was the first to use EUV right away. Went straight into into. Didn't work out; But it seems it is going in that direction. This new things that they did. In my opinion, it noteworthy. They did it before anyone. I gues like folding phones. Of course it din't work out at first, but why didn't any body else who claimed they had it release their phones? Probably because they get all their display parts from Samsung. There would be no Huawei without Samsung. They could buy it from their cousins at BOA. Go ahead and see how many people buy your phone.trivik12 - Tuesday, May 14, 2019 - link
Wait their S10 Soc was still 8nm(which was supposedly 10nm with some improvements) and so they are planning 7,6,5,4 and 3nm over next 2 years !!!!! Do we know if Note 10 SOC will atleast use 7nm EUV process.name99 - Wednesday, May 15, 2019 - link
Samsung claim that they started fabbing something (undisclosed) in high volume 7nm towards the end of 2018. There are a few reasonable possibilities, like Tesla (their chip is Samsung, nothing more disclosed) or maybe one of the various NN companies that have sprung up.5nm and 4nm are somewhat like 7nm+ and 7nm++, so reasonable products for say late 2019/early 2020 and mid 2021. Then 3nm late 2022. It's not an unreasonable schedule.
Samsung is not (as far as I know) discussing a 6nm. That's TSMC, for whom 6nm is more or less their 7nm++ for next year (7nm+ is this year's process). It will run in parallel with TSMC 5nm, but of course these are foundries --- part of their business model is to run simultaneously multiple processes at different performance/cost tradeoffs.
SaberKOG91 - Wednesday, May 15, 2019 - link
Don't forget that as EUV matures it will be involved in more of the process steps which is hopefully where a lot of these gains will come from. EUV was still extremely expensive when 7nm first launched to it was used in very few "bullet-proof" steps.Rudde - Wednesday, May 15, 2019 - link
Tesla NN-accelerator is 14nm.attila123 - Sunday, January 19, 2020 - link
You are taiwanese arn't you? You guys are funny. Samsung and Hynex was bust with their supercycle with their dram and nand chips. EVU Samsung went right into. TSMC Still using FINFIT. Just using EUV here and here. Don't get too Cocky dude. Samsung jsut went made a revolutionary feat which was in very much doubt. Stop being a troll because you are jealous. Just give them what they deserve. They accomplish something. That's it. You tone sucks and you're angy Samsung got there before Taiwan. EUV right away didn't work wout. But after the supercycle, they will cocentrate on the SOC which they already have. I didn't hear TSMC doing anything with EUV before Samsung brought it in. So just stop being a trollSychonut - Wednesday, May 15, 2019 - link
Looking forward to Intel's 14+++++.boeush - Wednesday, May 15, 2019 - link
Looking forward to Samsung's first subatomic-scale node.watersb - Wednesday, May 15, 2019 - link
Great write-up.I am really confused by these node names: how do they compare with Intel? What, exactly, is the "3 nanometer" aspect of the process?
Santoval - Wednesday, May 15, 2019 - link
They cannot be compared via nm numbers because these are purely marketing numbers. One more objective way of comparison is via transistor density, i.e. the number of transistors per mm^2. Even that can be fudged though, because for instance SRAM caches have different transistor density than the logic part of a chip.An ideal way of third party comparison of the density of different nodes would be to compare the density of the exact same chip (CPU or GPU) fabbed at say 14nm and 7nm. If you know the total number of transistors of the chips (which should be identical) you can then measure the bare dies to calculate their size (in square mm) and then divide the total transistor number by the die sizes to get the transistor density per mm^2.
HStewart - Wednesday, May 15, 2019 - link
In some ways you can think of Samsung 3nm here as Samsung 7nn++++. But the real determination is the number of transistors per size and speed between each device. Not sire if other foundries will have something similar to Intel Foreros which is not to confused with EMiB, where the die is 3d direction which increases the components in the vertical direction.I believe a storm is coming with this technology, it does not mean that this 3nm will be replace, but it could mean one of component in the Foreros package could be 3nm based - say if Samsung comes out with dense ram chips.I believe that Foveros is a revolution not evolution in technology. But it is designed to complement the process technology not replace it.
ajc9988 - Sunday, May 26, 2019 - link
Foveros is NOT a revolution. It is just 3D stacking. The most impressive part of it is the moving of a cache layer to the active interposer-ish base that the chiplets are attached to for it. Other than that, it is just the evolution of 2.5D, which AMD has had whitepapers detailing the analysis on cost of implementation back around November or December of 2017.So, to have something competitive, all they would need to do is incorporate components of their I/O die onto the active interposer and place HBM centrally stacked with the core chiplets around. Now, Intel being able to stack eDRAM for a level 4 cache sitting above the hotter components is a step forward, but other companies have looked into that as well and the entire industry has been moving toward that. They don't have a major lead on anyone in that regards. Also, they are only using it at first in extremely low power devices, which is where heat from core chiplets is easier to manage. Implementation in high performance chips will take more time because of that.
So, a 2.5D will likely be used in a high performance setting before 3D integrations. Whether Intel, AMD, or some other player will do so is just a matter of seeing who wins that race. But this isn't as revolutionary as you make it seem. It is an incremental step.
saratoga4 - Wednesday, May 15, 2019 - link
The names are marketing, they don't refer to any specific aspect of the process. We don't know how this will compare to Intel's nodes, they haven't said nearly as much as Samsung.psychobriggsy - Wednesday, May 15, 2019 - link
"The headline PPA values that Samsung is announcing are also impressive: compared to 7nm, 3GAE will offer 1.35x performance, 0.5x power, with a 0.65x die area."If the area is down 45%, then the die area is surely 0.55x, not 0.65x?
Also I guess that die area shrink is for the thinnest bridges. Ditto the power.
The 35% performance improvement is significant for a shrink these days. I guess that's for the widest bridges of course.
psychobriggsy - Wednesday, May 15, 2019 - link
Ah, 50% improvement for widest bridges, should have read on.Diogene7 - Wednesday, May 15, 2019 - link
I am wondering if those improvements are available all at the same time, or only separately one by one ?Ex:
1. Is it up to 35% performance improvement, OR up to 50% power decrease, OR up to 45% die area reduction ?
2. Is it for example 35% performance improvement, but in that case, there is no or little power decrease and there is no or little die area shrink ?
smilingcrow - Wednesday, May 15, 2019 - link
In other such releases it always seems to be OR and never AND.saratoga4 - Wednesday, May 15, 2019 - link
Power is nonlinear with performance, so 50% power decrease at isofrequency will mean a smaller decrease at higher frequency.attila123 - Sunday, January 19, 2020 - link
Yeah but different products have different uses. Maybe it need the temperature. Maybe it needs the power. Just because it mutually exclusive doesn't really mean anything. All I can say was this is the first crack at it. When you first did something were you the best? were you able to perfect everything there was; NO !!!! But Samsung just pulled off something extraordinary. Let's leave it at that. You have to remember people thought this was impossible. But they did it. That is what i am impressed with. I love computers. I majored in Econ, and it was a good major, but computer are the next revolution. Sometimes, I wished I studied computers.valinor89 - Wednesday, May 15, 2019 - link
It is funny when #SFF2019 is the tag for both the samsung event and a film festival.wrkingclass_hero - Thursday, May 16, 2019 - link
It's crazy, there was this standstill at 28nm, and another one at 14nm where it seemed like any further improvements would be minimal, yet here we are in a whirlwind of constant developments that seem to be coming faster and faster.s.yu - Thursday, May 16, 2019 - link
Not really, apparently 7nm would be 4x the density of 14nm right, that didn't happen, and this 3nm is not ~5.4x density of 7nm.The numbers are bumping, that's for sure.
attila123 - Sunday, January 19, 2020 - link
Yeah, but you're comparing Finfit which is the same technology to Gate all around. a quiet different technology. In addition, this is Beta 1. The important thing is that is was done. Something many thought was impossible. Comparing tow different technology is not fairattila123 - Sunday, January 19, 2020 - link
But this will break the law. Moors law, which is quiet significant. But i fully agree. Someone has to figure it out. The reward is the recognition, respect and of course the MONEY.