Intel Pentium 4 3.0C – The First 800MHz FSB CPU

What's in a faster FSB?

These next two pages are taken from our 800MHz FSB Sneak Peek article, if you haven't read through that already then contained within these pages is information relating to the practical benefits of an 800MHz FSB; if you have read the Sneak Peek article then we suggest skipping directly to the benchmarks.

Improving overall system performance is a game of removing bottlenecks and making paths that aren't already bottlenecked as fast as possible. When dealing with increasing the frequency of a FSB, there are two major factors that influence whether or not the faster FSB will actually improve performance.

The first factor is whether or not the transmit buffers on the FSB interface of the North Bridge (or MCH) will receive data fast enough to take advantage of the faster FSB. In order to understand this factor you have to have an understanding of how data flows from main memory into the chipset and finally to the CPU (and vice versa). When the CPU issues a read request onto the FSB, it sends the address of the data it needs in main memory onto the FSB. The address of the data needed is then forwarded on, via the FSB, to the chipset's FSB interface contained within the North Bridge, or in the case of the Pentium 4, the Memory Controller Hub (MCH). The FSB interface hands off the address to the memory controller, also contained within the North Bridge/MCH, and then the address request is sent to main memory and the North Bridge/MCH waits for the data at that address to be charged and ready to be sent from main memory. Once the data is ready, it is sent from main memory to the memory controller in the North Bridge/MCH, handed off to the FSB interface and then put on the FSB and sent to the CPU.

In the case of the Pentium 4's FSB, the actual operating frequency of the bus is 100/133MHz (for the 400 and 533MHz FSBs respectively). Addresses are sent twice per clock, which makes the FSB transfer addresses as fast as a 200/266MHz FSB would; and finally we have the quad-pumped data transfer rates, which means that data can be sent 4x per clock, effectively making the FSB transfer data as fast as a 400/533MHz FSB would. Since data, not address, transmission is what eats up the majority of FSB bandwidth, Intel gets away with calling the Pentium 4's FSB a 400/533MHz FSB. With the forthcoming 800MHz FSB, addresses will be transferred at 400MHz and data will be sent at 800MHz. What's interesting to note is that addresses will be transferred on the new FSB as fast as data was sent on the first Pentium 4 FSB introduced back in 2001.

Back to the original point however, if the North Bridge/MCH isn't able to get data from main memory as quickly as it can send it through the FSB then there's no point to increasing the FSB frequency. Think of it like this; let's say you had a highway going straight into a mall, with an identical highway going straight out of the mall. Both highways have the same number of lanes and initially they have the same 45mph speed limit. Now let's say that there's a great deal of traffic flowing in and out of the mall and in order to get more people in and out of the mall quicker, the department of transportation agrees to increase the speed limit of the highway going into the mall from 45mph to 70mph; the speed limit of the highway leaving the mall is still stuck at 45mph. While more people will be able to reach the mall quicker, there will still be a bottleneck in the parking area leaving the mall - since the increased number of people that are able to get to the mall still have to leave at the same rate. This is equivalent to increasing the FSB frequency but leaving the memory frequency/bandwidth unchanged on a chipset, you're speeding up one part of the equation while leaving the other part untouched.

In this case, the focus is more on balancing FSB and memory bandwidth rather than frequencies (although it is important to have frequencies that are in sync with one another in order to keep latencies as low as possible). The Pentium 4 features a 64-bit wide FSB interface, and we've already explained the frequencies this FSB can run at. Simple multiplication shows us that the 533MHz FSB can offer a maximum of 4.264GB/s of bandwidth. The 845PE chipset has a 64-bit DDR333 memory interface, offering a maximum of 2.664GB/s of memory bandwidth, and the 850E chipset has a 32-bit PC1066 RDRAM memory interface that provides at most 4.264GB/s of memory bandwidth. As you can see just by looking at the bandwidth numbers, the 850E chipset is perfectly balanced for the amount of bandwidth offered by the 533MHz FSB, which is why it is significantly faster than the 845PE.

The 800MHz FSB will offer no less than 6.4GB/s of bandwidth, which would require either a 32-bit PC1600 RDRAM memory interface (note that the PC1600 standard does not exist) or a 64-bit DDR800 memory interface (also a non-existant memory technology). Well, if you can't get faster memory, you widen the memory interface in order to increase bandwidth. Remember that bandwidth is the product of bus width and transfer rate, so if you can't improve the transfer rate, you increase the width of the bus. In the case of the upcoming 865 and 875 chipsets, Intel took the 64-bit DDR memory interface of the 845PE chipset and added a second 64-bit channel along with adding DDR400 support. A 128-bit memory interface (2 x 64-bit channels) with DDR400 memory now offers exactly 6.4GB/s of memory bandwidth, perfectly balanced with the 800MHz FSB, without using exotic memory technology or speeds that aren't readily available.

With an increase in both the FSB frequency and memory bandwidth, the performance will not be hindered by bottlenecks in the platform itself, but we still have to ask the question of whether or not the CPU can benefit…